Before an integrated circuit is fabricated, it is first designed by simulating the operation of the proposed circuits that are to be included within the integrated circuit. Simulation is used to verify correct functional operation of the circuit, as well as to verify correct dynamic timing operation. when two signal lines on a integrated circuit are physically adjacent there is a capacitance between the signal lines that may cause signal interference due to signal coupling.
A commonly used simulator for designing integrated circuits is SPICE, which is available from the University of California at Berkeley, via the Department of Electrical Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets may be 40,000 in a typical integrated circuit design. Secondly, for each such net, about seventy discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a ladder circuit which has about two dozen nodes; with each node having a resistor to the next node, a capacitor to ground, and a capacitor to any adjacent signal line.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, about 1,000 increments of ten picoseconds each are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment the SPICE program repetitively solves a matrix equation which is of the form [Y][V]=[l]. Here, Y is an n-x-n matrix, V is an nx1 matrix, and I is an nx1 matrix; where n is the number of nodes in the circuit. Thus, for a single victim net with twenty aggressor nets, n is (24 nodes per net).times.(21 nets) or 504.
For each increment in time.sub.1 the SPICE program makes about five iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments.
Using a state of the art workstation, it takes about ten minutes to perform a SPICE simulation of a single circuit which has 500 nodes and for which a solution is sought for 1,000 time increments. Such a circuit represents a typical victim net with twenty aggressor nets. Consequently, to simulate a chip which has 40,000 nets would take about 400,000 minutes, or more than 270 days to complete!
Accordingly, a primary object of the present invention is to provide a method of designing circuit chips by which the above problems are overcome.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.